1. Field of the Invention
The present invention relates to an analog-to-digital (AD) conversion circuit, which converts an analog signal into digital data, and a solid-state image pickup device having the same.
Priority is claimed on Japanese Patent Application No. 2012-187723, filed Aug. 28, 2012, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
As an example of an AD conversion circuit used in a solid-state image pickup device of the related art, a configuration illustrated in FIG. 8 (for example, see Japanese Unexamined Patent Application, First Publication No. 2012-039386) is well known. First, a configuration and an operation of the AD conversion circuit illustrated in FIG. 8 will be described. The AD conversion circuit illustrated in FIG. 8 includes a comparison unit 11, a signal generation unit 12, a latch unit 13, a count unit 14, and a delay unit 15.
The delay unit 15 includes a plurality of delay units DU[0] to DU[7], each of which delays and outputs an input signal. A start pulse (=Start_P) is input to the leading delay unit DU[0]. The comparison unit 11 receives an analog signal Signal serving as a time detection target and ramp waves Ramp that decrease with the passage of time, and outputs an output signal CO indicating a result obtained by comparing the analog signal Signal to the ramp waves Ramp. In the comparison unit 11, a time interval (a magnitude of a time-axis direction) corresponding to an amplitude of the analog signal Signal is generated.
The signal generation unit 12 includes an inverting delay circuit DLY that inverts and delays the output signal CO, and an AND circuit AND1 that outputs an output signal Hold_L obtained by performing an AND operation on the output signal CO and an output signal xCO_D of the inverting delay circuit DLY. The latch unit 13 includes latch circuits D—0 to D—7, which latch logic states of output signals CK0 to CK7 of the delay units DU[0] to DU[7] of the delay unit 15. In addition, the latch unit 13 includes an AND circuit AND2 which outputs an output signal Hold_C obtained by performing the AND operation on the output signal xCO_D of the inverting delay circuit DLY of the signal generation unit 12 and a control signal Enable to the latch circuit D[7]. The count unit 14 includes a counter circuit which performs a count operation based on the output signal CK7 from the delay unit 15 via the latch circuit D—7.
The latch circuits D—0 to D—6 are in the enable (valid) state when an output signal Hold_L is in a high state (logic value “1”), and output the output signals CK0 to CK6 of the delay units DU[0] to DU[6]. In addition, the latch circuits D—0 to D—6 are in a disable (invalid) state when the output signal Hold_L is in a low state (logic value “0”), and latch the logical states corresponding to the output signals CK0 to CK6 of the delay units DU[0] to DU[6].
The latch circuit D—7 is in the enable (valid) state when the output signal Hold_C is in the high state, and outputs the output signal CK7 of the delay unit DU[7]. In addition, the latch circuit D—7 is in the disable (invalid) state when the output signal Hold_C is in the low (L) state, and latches the logical state corresponding to the output signal CK7 of the delay unit DU[7].
Although a count latch circuit, which latches a logic state of a count result of the count unit 14, is not illustrated, a counter circuit having a latch function is used and hence the count unit 14 also serves as the count latch circuit.
Next, an operation of the example of the related art will be described. FIG. 9 illustrates the operation of the AD conversion circuit according to the example of the related art. In FIG. 9, Q0 to Q7 denote signals output from the latch circuit D—0 to D—7.
First, at a timing (first timing) relating to a comparison start in the comparison unit 11, a clock having a cycle approximately consistent with a delay time (a sum of delay times of 8 delay units DU[0] to DU[7]) of the delay unit 15 is input as the start pulse (=Start_P) to the delay unit 15. Thereby, the operation of the delay unit 15 is started. The delay unit DU[0] constituting the delay unit 15 outputs the output signal CK0 by delaying the start pulse (=Start_P), and the delay units DU[1] to DU[7] constituting the delay unit 15 output the output signals CK1 to CK7 by delaying the output signals of previous-stage delay units, respectively. The output signals CK0 to CK7 of the delay units DU[0] to DU[7] are input to the latch circuits D—0 to D—7 of the latch unit 13. At this time, because the output signal CO of the comparison unit 11 is in the low state and the output signal xCO_D of the inverting delay circuit DLY is in the high state, the output signal Hold_L of the AND circuit AND1 of the signal generation unit 12 is in the low state, the latch circuits D—0 to D—6 are in the disable state, and operations thereof are stopped.
On the other hand, because the output signal xCO_D of the inverting delay circuit DLY is in the high state and the control signal Enable is in the high state, the output signal Hold_C of the AND circuit AND2 of the latch unit 13 is in the high state and the latch circuit D—7 is in the enable state. The latch circuit D—7 directly outputs the input output signal CK7 of the delay unit DU[7] to the count unit 14.
The count unit 14 performs a count operation based on the output signal CK7 of the delay unit DU[7] output from the latch circuit D—7 of the latch unit 13. In this count operation, a count value is increased or decreased by the rising or falling of the output signal CK7.
At a timing (second timing) at which a signal voltage of the analog signal Signal is approximately consistent with that of the ramp waves Ramp, an output signal CO of the comparison unit 11 is inverted, and the output signal Hold_L of the AND circuit AND1 of the signal generation unit 12 is in the high state. Thereby, the latch circuits D—0 to D—6 are in the enable state. After a time consistent with a delay time of the inverting delay circuit DLY of the signal generation unit 12 has elapsed from the second timing (third timing), the output signal xCO_D of the inverting delay circuit DLY of the signal generation unit 12 is inverted and the output signal Hold_L of the AND circuit AND1 of the signal generation unit 12 is in the low state. Thereby, the latch circuits D—0 to D—6 are in the disable state. At this time, the logic states corresponding to the output signals CK0 to CK6 of the delay units DU[0] to DU[6] are latched in the latch circuits D—0 to D—6. In addition, because the output signal Hold_C of the AND circuit AND2 of the latch unit 13 is in the low state at the third timing, the latch circuit D—7 is in the disable state and the logic state corresponding to the output signal CK7 of the delay unit DU[7] is latched in the latch circuit D—7.
The operation of the latch circuit D—7 is stopped and thus the count unit 14 latches a count value. Digital data corresponding to the analog signal Signal is obtained by the logic state latched by the latch unit 13 and the count value latched by the count unit 14.
In accordance with the AD conversion circuit according to the above-described example of the related art, current consumption of the latch unit can be reduced, and current consumption of the AD conversion circuit can be reduced, because the latch circuits D—0 to D—6 operate in only a period from the second timing to the third timing.
Because the signal Hold_L for controlling operations of the latch circuits D—0 to D—6 and the signal Hold_C for controlling the operation of the latch circuit D—7 are generated by separate AND circuits in the above-described AD conversion circuit of the related art, it is difficult to accurately latch an input signal, and there is a possibility of an error occurring in the AD conversion result and AD conversion accuracy being degraded if there is a deviation in the timing of switching between the high state and the low state between the signal Hold_L and the signal Hold_C due to variation in a delay of an input signal or a circuit threshold voltage in the AND circuits AND1 and AND2 and variation in an operation speed when an edge at which pulses of the output signals CK0 to CK7 of the delay units DU[0] to DU[7] are switched from the low state to the high state is close to the output signals CK6 and CK7.
Hereinafter, the case in which the AD conversion accuracy is degraded will be described. FIG. 10 illustrates the case in which operation timings of the AND circuit AND1, which outputs the signal Hold_L, and the AND circuit AND2, which outputs the signal Hold_C, are deviated by Δt. In this case, because a difference between the timing at which the signal Hold_L is switched from the high state to the low state and the timing at which the signal Hold_C is switched from the high state to the low state is Δt, a difference between the timing at which the latch circuits D—0 to D—6 latch the output signals CK0 to CK6 of the delay units DU[0] to DU[6] and the timing at which the latch circuit D—7 latches the output signal CK7 of the delay unit DU[7] is Δt.
Thereby, the latch result of the latch circuits D—0 to D—7 becomes a binary number (10011100)2=(D—7=1, D—6=0, D—5=0, D—4=1, D—3=1, D—2=1, D—1=0, and D—0=0) (“0” corresponds to the low state and “1” corresponds to the high state). In this case, the number of positions of switching from 0 to 1 (or from 1 to 0) in the latch result of the latch circuits D—0 to D—7 is 2. On the other hand, when the latch circuit D—7 latches the output signal CK7 at the same timing as the latch circuits D—0 to D—6, the latch result of the latch circuits D—0 to D—7 becomes a binary number (00011100)2=(D—7=0, D—6=0, D—5=0, D—4=1, D—3=1, D—2=1, D—1=0, and D—0=0). In this case, the number of positions of switching from 0 to 1 (or from 1 to 0) in the latch result of the latch circuits D—0 to D—7 is 1.
When an encoder which performs encoding according to a position of switching from 0 to 1 (or from 1 to 0) in the latch result of the latch circuits D—0 to D—7 is used, two switching positions are the cause of erroneous encoding, and an error of one or more least significant bits (LSB) is likely to occur.